1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device including a memory cell array area and a peripheral circuit area.
2. Description of Related Art
A DRAM (Dynamic Random Access Memory) device generally includes a memory cell array area in which a plurality of memory cells are arranged in a two-dimensional array, and a peripheral circuit area in which a peripheral circuit for driving the memory cells is disposed. The memory cells each include a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) formed in the surface region of a semiconductor substrate, and a cell capacitor overlying the MOSFET for storing therein electric charge or data.
In a process for manufacturing the DRAM device, a gate insulation film is first for on a semiconductor substrate, followed by consecutively depositing thereon a silicon electrode film and an overlying protective film. A photolithographic and etching process is then conducted to pattern the gate insulation film, silicon electrode film and overlying protective film, to configure part of a gate electrode structure. Impurities are then implanted in the surface region of the semiconductor substrate by an ion-implantation technique using the patterned gate electrode structure as an implantation mask, thereby forming source/drain regions of the MOSFETs. A heat treatment is then performed to diffuse and activate the implanted impurities, thereby forming MOSFETs including the gate electrode and associated source/drain regions. Patent Publication JP-2006-120832A, for example, describes a DRAM device and a method for manufacturing the same.
The electric charge stored in the cell capacitors gradually decreases as the time elapses due to a junction leakage current flowing across the p-n junction in the MOSFETs. Accordingly, a refresh operation is generally performed periodically, wherein the stored electric charge is read out from the cell capacitors within a specific time interval to be stored again in the cell capacitors. There is a strong demand of a longer refresh time interval in the DRAM device for reducing the power dissipation thereof as by suppressing the junction leakage current. For this purpose, it is preferable that the source/drain regions in the memory cell array area have a lower electric-field strength across the p-n junction by employing a lower impurity concentration, and that the impurity level be lowered in the vicinity of the p-n junction by using a longer-time and higher-temperature heat treatment.
On the other hand, it is preferable in the peripheral circuit area that the impurity concentration in the source/drain regions be higher and that the channel length be smaller to accelerate the response speed, due to a strong demand for a higher operational speed thereof, differently from the source/drain regions in the memory cell array area. It is noted here by the inventor that the longer-time and higher-temperature heat treatment, employed for the sake of the memory cell array area, will inevitably diffuse the impurities excessively in the source/drain regions in the peripheral circuit area, thereby causing a short channel effect to degrade the transistor characteristics of the MOSFETs in the peripheral circuit area. Hence, it is desired that the heat treatment conducted for the memory cell array area do not excessively diffuse the impurities in the source/drain regions in the peripheral circuit area, to thereby suppress degradation of the transistor characteristics of the MOSFETs in the peripheral circuit area.